Method for forming a conductive plug of a semiconductor device

ABSTRACT

Embodiments relate to a method for forming a conductive plug of a semiconductor device that may include preparing a semiconductor substrate having multilayer metal interconnections, forming interlayer insulating layers above the semiconductor substrate, etching part of each interlayer insulating layer such that each multilayer metal connection is exposed, and forming a via hole, depositing a conductive layer such that the via hole is filled, and performing chemical mechanical polishing (CMP) on the conductive layer such that each interlayer insulating layer is exposed, and forming the plug. The step of performing the CMP on the conductive layer may be performed using a polishing pad having a polishing speed of about 3200 angstroms/min to about 5000 angstroms/min.

The present application claims priority under 35 U.S.C. 119 and 35U.S.C. 365 to Korean Patent Application No. 10-2005-0134061 (filed onDec. 29, 2005), which is hereby incorporated by reference in itsentirety.

BACKGROUND

As semiconductor devices have become more highly integrated, technologyfor forming a multilayer interconnection may become more important. Tovertically and electrically connect multilayer metal interconnections,technology for forming a conductive plug may also be important. Aconductive plug may be made of tungsten (W), which may have excellentconductivity and interlayer filling characteristics.

The conductive plug may be formed by filling a conductive layer suchthat a contact hole or a via hole may be filled. The filled conductivelayer may then be planarized.

A method of planarizing the filled conductive layer may include anetch-back technique and a chemical mechanical polishing (CMP) technique.Hence, the conductive layer may be planarized by a CMP technique. Athickness and CMP conditions of the conductive layer may be variedaccording to each level (or each layer).

Further, the conductive plug may have different integration densitiesaccording to a stacked level. In other words, the conductive plugconnecting a semiconductor substrate and a primary interconnection mayhave a very high integration density. For a conductive plug connectingneighboring upper interconnections, the higher the metal interconnectiongoes, the lower the integration density becomes, as in the purpose ofthe multilayer metal interconnection. This means that the conductiveplug connecting the upper interconnections may connect with severalmetal interconnections, and thus may be very important.

The upper conductive plugs connecting the interconnections,particularly, the fifth plug connecting the fourth and fifth metalinterconnections and the sixth plug connecting the fifth and sixth metalinterconnections, may have a pattern-dependent defect. This may be knownas a black hole defect, and may occur on their surfaces.

This pattern-dependent defect may cause contact failure with the metalinterconnection that may be formed later. Electrical reliability of thesemiconductor device may thus be lowered. Moreover, device malfunctionmay occur.

The pattern-dependent defect may be attributed to pattern density, i.e.integration density, of the plug (as indicated by its name), and may begenerated at a portion where the pattern density is relatively low.

The pattern-dependent defect may become more serious on a surface of anedge of the plug, compared to a center of the plug.

Various causes and distributions of the pattern-dependent defect havebeen identified.

For example, the pattern-dependent defect may occur when a pad for arelatively low polishing speed is used. Such a pad may be, for example,a Rodel pad. In this example, the use of the pad having a low polishingspeed may make a CMP time longer.

For this reason, a plug of a low-integration-density portion, where theinterlayer insulating layer is exposed relatively quickly, may undergo aCMP for a longer time than the plug of a high-integration-densityportion. The above-described defect may therefore occur. Here, as wellknown as the micro-loading effect, the low-integration-density portionmay have relatively fast etching and polishing speeds as compared to thehigh-integration-density portion.

Because the Rodel pad may have a relatively low polishing speed (3000angstroms or less per minute), a corresponding CMP process may give riseto the pattern-dependent defect, i.e. the black hole defect.

The portion where the integration density is relatively low may be anisolation region. When the isolation region and the pattern dense area(e.g. the cell region) are subjected to the CMP at the same time, aconductive plug may first be formed on the isolation region.

Further, the Rodel pad may have a porous structure in order to increasea chemical reaction effect between slurry and a wafer, and thus may haverelatively small pores, each of which may have a size of about 50 μm toabout 120 μm.

However, because the Rodel pad may have a plurality of pores, it mayhave low absorbing efficiency of the slurry. Hence, a large quantity ofslurry and a large quantity of chemical may be required. If the CMPprocess is performed for a long time under the conditions where arelatively large quantity of slurry and chemical are required, theconductive plug (formed on the low integration density portion) at whichthe interlayer insulating layer is relatively fast exposed may be morequickly lost.

Moreover, a pattern-dependent defect may cause a top surface of theconductive plug to be dented.

If denting occurs, the dented portion may allow residues such as slurryparticles, tungsten materials, and oxide materials generated during thepolishing process to be left behind. This may be responsible for anincrease of contact resistance and contact failure during subsequentmetallization processes.

In addition, the pattern-dependent defect may occur because an edgeportion of the via hole may have a conductive layer deposited to be lessthan the center of the via hole. Furthermore, during the CMP process,the edge may have a polishing speed faster than that of the center, andthus may be oxidized relatively faster. Hence, a pattern-dependentdefect may occur.

SUMMARY

Embodiments relate to a method for forming a conductive plug of asemiconductor device.

Embodiments relate to a method for forming a conductive plug of asemiconductor device that may be capable of preventing pattern-dependentdefect on a surface of the conductive plug that may be formed at aportion having relatively low integration density.

Embodiments relate to a method for forming a conductive plug of asemiconductor device that may be capable of preventing a so-called blackhole defect occurring on the surface of a tungsten plug during achemical mechanical polishing (CMP) process for forming the tungstenplug connecting between upper interconnections.

According to embodiments, a method for forming a conductive plug of asemiconductor device may include preparing a semiconductor substratehaving multilayer metal interconnections, forming interlayer insulatinglayers above the semiconductor substrate, etching part of eachinterlayer insulating layer such that each multilayer metal connectionis exposed, and forming a via hole, depositing a conductive layer suchthat the via hole is filled, and performing chemical mechanicalpolishing (CMP) on the conductive layer such that each interlayerinsulating layer is exposed, and forming the plug. The step ofperforming the CMP on the conductive layer may be performed using apolishing pad having a polishing speed of about 3200 angstroms/min toabout 5000 angstroms/min.

According to embodiments, a method for forming a conductive plug of asemiconductor device may include preparing a semiconductor substratehaving multilayer metal interconnections, forming interlayer insulatinglayers above the semiconductor substrate, etching part of eachinterlayer insulating layer such that each multilayer metal connectionis exposed, and forming a via hole, depositing a conductive layer suchthat the via hole is filled, performing chemical mechanical polishing(CMP) on the conductive layer such that each interlayer insulating layeris exposed, and forming the plug, and cleaning a surface of the plug.The step of cleaning the surface of the plug includes the sub-steps of:removing primary residues from the surface of the plug, removing oxidecomponents from the surface of the plug, and removing secondary residuesfrom the surface of the plug.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 and 2 are example sectional diagrams illustrating a conductiveplug of a semiconductor device and a method for forming a conductiveplug of a semiconductor device according to embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS

Referring to FIG. 1, semiconductor substrate 100 having multilayer metalinterconnections M1 to M4 may be prepared.

Although not illustrated in the drawings, semiconductor substrate 100may include metal oxide semiconductor (MOS) transistors, and the metalinterconnections may be connected with gates of the MOS transistors.

According to embodiments, first, second, third, and fourth metalinterconnections M1, M2, M3, and M4 may be formed. The multilayer metalinterconnections M1 to M4 may be insulated by interlayer insulatinglayers 110, 120 and 130, each of which may be interposed between the twoneighboring metal interconnections.

Further, first metal interconnection M1 may be electrically connectedwith second metal interconnection M2 using first plug V1. Second metalinterconnection M2 may be electrically connected with third metalinterconnection M3 using second plug V2. Third metal interconnection M3may be electrically connected with fourth metal interconnection M4 usingthird plug V3.

Interlayer insulating layer 140 may be deposited on the result ofsemiconductor substrate 100 having fourth metal interconnection M4.Interlayer insulating layer 140 may be etched such that fourth metalinterconnection M4 is exposed. This may form via hole h.

Tungsten metal layer 150 may be deposited having a prescribed thicknesssuch that the via hole h may be filled.

Referring to FIG. 2, a chemical mechanical polishing (CMP) process maybe carried out such that the tungsten metal layer 150 may be filled inthe via hole h, thereby forming a fourth tungsten plug 155.

In embodiments, the CMP process may be carried out using a pad having apolishing speed of 3200 angstroms or more per minute. In embodiments,the polishing speed may be 3200 angstroms per minute to 5000 angstromsper minute. Such conditions may include a TWI pad.

As described above, when the pad having a relatively high polishingspeed is used, an overall processing time may be reduced by 20 secondsor more. Thus, although the conductive plug of an isolation region maybe exposed relatively quickly, the time when the conductive plug isexposed to slurry may be reduced. Thus, a pattern-dependent defect maybe reduced.

Further, although the center of the plug may have a thickness partiallydifferent from a thickness of an edge of the plug, and although thepolishing speed of the edge of the plug may be relatively fast, theoverall polishing speed may be improved, so that differences between thethicknesses and between polishing uniformities may not exert a greatinfluence on the pattern-dependent defect.

In addition, the TWI pad may be relatively large, and may have a poresize of about 80 μm to about 120 μm. Moreover it may have a internalstructure of a fabric. In this manner, when the inside of the pad hasthe relatively large pore size and the fabric structure, the TWI pad mayhave slurry absorptance higher than a related art Rodel pad. Hence, asupplied quantity of chemical may be reduced. Accordingly, thus defectsthat may be caused by a large quantity of slurry and chemical may beprevented.

As described above, after fourth tungsten plug 155 may be formed, acleaning process may be performed to remove impurities that may be occuron a surface of fourth tungsten plug 155.

According to embodiments, the cleaning process may include removingprimary residues such as metal residues or slurry residues. The processmay also include removing oxide components, and removing secondaryresidues. Accordingly, the process may be able to remove all metalresidues, slurry residues, and parasite oxide components that may occuron the surface of fourth tungsten plug 155.

In embodiments, the step of removing the residues may be accomplished bythe cleaning process using a solution of NH₄OH, and the step of removingthe oxide components may be accomplished by the cleaning process using asolution of HF.

In embodiments, all of the residues, including the oxide componentsoccurring on the surface of fourth tungsten plug 155, may be removed bythe NH₄OH/HF/NH₄OH cleaning processes. This may prevent the occurrenceof the black hole defect and the contact failure.

It should be understood that embodiments are not limited to the abovedescribed process.

For example, in embodiments, any pad may be used if its polishing speedand internal structure are adequate. In embodiments, any pad having apolishing speed of more than approximately 3200 angstroms/min with aninternal fabric structure may be used.

Further, although the cleaning process of this embodiment may be carriedout by the three steps (e.g. the residue removing step, the oxidecomponent removing step, and the residue removing step), other cleaningprocesses could be used. For example, in embodiments only the residueremoving step and the oxide component removing step may be used.Furthermore, the cleaning process may be applied to all the conductiveplugs including the fourth conductive plug.

In embodiments, any material may be used for the plug material in placeof tungsten, so long as it has adequate conductivity and interlayerfilling characteristics.

Moreover, in embodiments this process may be used on any plug inaddition to the fourth plug, so long as it can connect the upper metalinterconnections more than the fourth metal interconnection.

In embodiments, this process may be used on any low density region inaddition to the isolation region. For example, the low integrationdensity region may include a core and its surrounding circuit of thesemiconductor device other than the isolation region.

In embodiments, when the via plug connecting between the metalinterconnections, for example between the upper metal interconnections(more than the fourth metal interconnection), may be formed, the CMPprocess may be performed using the polishing pad having the polishingspeed of 3200 angstroms/min or more, a relatively large pore size, andan internal fabric structure.

According to embodiments, the use of a polishing pad having a relativelyfast polishing speed may allow the CMP process to be performedirrespective of the pattern density. Accordingly, it may be possible toprevent the defects from occurring on the surface of the plug within theregion, such as the isolation region, where the plugs are sparselyformed. Further, due to the increase of the polishing speed, thepolishing difference between the center and the edge of the plug may bereduced.

In embodiments, the use of the polishing pad having a large pore sizeand a fabric structure may improve the absorptance of slurry.Accordingly, a quantity of supplied chemical and the slurry may bereduced. Hence, a surface defect caused by the slurry may be reduced.

In embodiments, after the conductive plug may be formed, certainresidues, including the oxide components, that may occur on the surfaceof the tungsten plug may be removed by the NH₄OH/HF/NH₄OH cleaningprocesses. This may further reduce the occurrence of the black holedefect.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to embodiments. Thus, it isintended that embodiments cover modifications and variations thereofwithin the scope of the appended claims. It is also understood that whena layer is referred to as being “on” or “over” another layer orsubstrate, it can be directly on the other layer or substrate, orintervening layers may also be present.

1. A method comprising: forming a conductive layer an over an interlayerinsulating layer, the conductive layer filling a via hole formed in theinterlayer insulating layer; performing chemical mechanical polishing(CMP) on the conductive layer to expose the interlayer insulating layerand form the plug, wherein CMP is performed on the conductive layerusing a polishing pad having a polishing speed of at least 3200angstroms/min.
 2. The method of claim 1, wherein performing the CMP onthe conductive layer is performed using a polishing pad having apolishing speed of about 3200 angstroms/min to about 5000 angstroms/min.3. The method of claim 1, further comprising: preparing a semiconductorsubstrate having multilayer metal interconnections; forming aninterlayer insulating layer above the semiconductor substrate; etchingpart of the interlayer insulating layer such that at least onemultilayer metal connection is exposed, and forming the via hole;depositing the conductive layer over the interlayer insulating layersuch that the via hole is filled.
 4. The method of claim 1, wherein thepolishing pad comprises pores having a diameter of about 80 μm to about120 μm,
 5. The method of claim 4, wherein an internal structure of thepolishing pad comprises a fabric.
 6. The method of claim 1, wherein themetal interconnection exposed by the via hole is at least a fourth metalinterconnection.
 7. The method of claim 6, wherein the metalinterconnection exposed by the via hole comprises a fourth-layer metalinterconnection.
 8. The method of claim 1, wherein the conductive layercomprises tungsten.
 9. The method of claim 1, further comprisingcleaning a surface of the plug after forming the plug.
 10. The method ofclaim 9, wherein cleaning the surface of the plug comprises removingresidues from the surface of the plug and removing oxide components fromthe surface of the plug.
 11. The method of claim 10, wherein removingthe residues comprises cleaning with a solution of NH₄OH, and removingthe oxide components comprises cleaning with a solution of HF.
 12. Themethod of claim 10, further comprising removing residues after removingthe oxide components.
 13. A method comprising: preparing a semiconductorsubstrate having multilayer metal interconnections; forming at least oneinterlayer insulating layer above the semiconductor substrate; etchingpart of the at least one interlayer insulating layer to form at leastone via hole exposing at least one multilayer metal connection;depositing a conductive layer over the least one interlayer insulatinglayer such that the at least one via hole is filled; performing chemicalmechanical polishing (CMP) on the conductive layer such that the atleast one interlayer insulating layer is exposed to form a plug; andcleaning a surface of the plug by removing primary residues from thesurface of the plug and removing oxide components from the surface ofthe plug.
 14. The method of claim 13, further comprising removingsecondary residues from the surface of the plug after removing oxidecomponents from the surface of the plug.
 15. The method of claim 14,wherein removing the residues comprises cleaning with a solution ofNH₄OH, and removing the oxide components comprises cleaning with asolution of HF.
 16. The method of claim 13, wherein the CMP is performedusing a polishing pad comprising pores having a diameter ofapproximately 80 μm to about 120 μm, and wherein an internal structureof the polishing pad comprises fabric.
 17. The method of claim 13,wherein performing the CMP on the conductive layer is performed using apolishing pad having a polishing speed of at least 3200 angstroms/min.18. The method of claim 13, wherein performing the CMP on the conductivelayer is performed using a polishing pad having a polishing speed ofapproximately 3200 angstroms/min to approximately 5000 angstroms/min.19. The method of claim 13, wherein the metal interconnection exposed bythe at least one via hole is at least a fourth metal interconnection.20. The method of claim 19, wherein the metal interconnection exposed bythe via hole comprises a fourth-layer metal interconnection.